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r5101g series microprocessor power management with watchdog timer no. ea-071-100128 1 outline the r5101g series are cmos-based con power m anagement ics with high accuracy output voltage and detector threshold and with ultra low supply current. each of these ics consists of a voltage regulator, a voltage detector and a watchdog timer. thus, the r5101g se ries have the function of a power management for microprocessor, a monitor of the voltage of a power source and a micr oprocessor supervisor. the built-in voltage regulator with an internal driver tr ansistor can supply typically 50ma current to a system when the voltage difference between input and output is 2v. therefore these ics are very suitable for various power supply systems for microprocesso rs. the output voltage is monitored by the voltage detector which is built-in these ics. the built-in voltage detector has an output delay fu nction and the delay time can be set by an external capacitor (c d ). the output voltage and the detector threshold voltage can be set individually for each ic by laser trimming. furthermore, when a microprocessor works incorr ectly, the watchdog timer which checks over microprocessor generates reset signal s intermittently to prevent a w hole system from being malfunction. the timeout periods for watchdog and reset can also be set individually by an external capacitor (c tw ). features ? built-in a watchdog timer ? timeout period for watchdog and generating a reset signal can be set by an external capacitor ? watchdog timer can be stopped individually by ce pin ? supply current .................................................................. typ. 5a ? the output voltage of voltage regulator and the detecto r threshold voltage can be set individually with a step of 0.1v for each ic by laser-trim. ? high accuracy output voltage of voltag e regulator and detector threshold 2.5% ? power-on reset delay time can be set by an external capacitor ? output current ................................................................. typ. 50ma (at v in ? v out =2v) ? package........................................................................... ssop-8g applications ? power source fo r microprocessors
r5101g 2 block diagrams r5101gxxxa level shift vref2 wdt 8 reset 3 c tw 7 ce 2 c d 1 sck 4v dd 5v ou t 6gn d vref1 selection guide the output voltage and the detector threshold for t he ics can be selected at the users? request. product name package quantity per reel pb free halogen free R5101GXXXA-TR ssop-8g 3,000 pcs yes yes xxx: the combination of output volt age and detector threshold fo r each channel can be designated by serial numbers. (for details, please refer to mark informations.)
r5101g 3 pin configuration ? ssop-8g 1 2 3 4 8 7 6 5 pin descriptions pin no. symbol description 1 sck clock input pin from microprocessor 2 c d external capacitor pin for setting delay time of voltage detector 3 c tw external capacitor pin for setting reset and watchdog timeout periods 4 v dd power supply pin 5 v out output pin for voltage regulator 6 gnd ground pin 7 ce control switch pin for watchdog timer ("h" active, "l" inactive) 8 reset output pin for reset signal of watchdog timer and voltage detector. (output type is nch open drain, output "l" at detecting detector threshold and watchdog timer reset.)
r5101g 4 absolute maximum ratings topt = 25 c, v ss = 0v symbol item rating unit v dd supply voltage ? 0.3 to 12 v v cd voltage of c d pin v ss ? 0.3 to v dd + 0.3 v v ctw voltage of c tw pin v ss ? 0.3 to v dd + 0.3 v v out voltage of v out pin v ss ? 0.3 to v dd + 0.3 v v re s et output voltage voltage of reset pin v ss ? 0.3 to 12 v v ce voltage of ce pin v ss ? 0.3 to v dd + 0.3 v v sck input voltage voltage of sck pin v ss ? 0.3 to v dd + 0.3 v i out current of v out pin 150 ma i reset output current current of reset pin 10 ma p d power dissipation (ssop-8g) ? 380 mw t opt operating temperature range ? 40 to 85 c t stg storage temperature range ? 55 to 125 c ? ) for power dissipation, please refer to package information. absolute maximum ratings electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause the permanent damages and may degrade the life time and safe ty for both device and sy stem using the device in the field. the functional operation at or over these absolute maximum ratings is not assured.
r5101g 5 electrical characteristics ? r5101gxxxa topt = 25 c symbol item conditions min. typ. max. unit v dd operating voltage 1.5 10 v i ss -on supply current (wdt active) v dd =ce=v out +2.0v 5 15 a i ss -off supply current (wdt inactive) v dd =v out +2.0v, ce=gnd 6 18 a v out output voltage v dd =v out +2.0v, i out =10ma 0.975 1.025 v i out output current ? 1 v dd =v out +2.0v 50 ma v dif dropout voltage refer to the following table v out / i out load regulation v dd =v out +2.0v, 1ma i out 30ma (in case that 3.0v v out 5.0v, 1ma i out 50ma) 50 100 mv v out / v dd line regulation i out =10ma v out +0.5v v dd 10v 0.1 0.2 %/v i lim current limit (short mode) v out =gnd 10 50 100 ma v out / t opt output voltage temperature coefficient i out =10ma -40 c t opt 85 c 100 ppm/ c -v det detector threshold 0.975 1.025 v v hys hysteresis range -v det 0.03 -v det 0.05 -v det 0.07 v v detmgn regulator voltage margin against released voltage v out -((-v det )+v hys ), i out =10ma 0.02 v -v det / t opt detector threshold temperature coefficient -40 c t opt 85 c 100 ppm/ c t pr reset delay time v dd =v out +2.0v, c d =0.001f 7 14 35 ms t wd watchdog timeout period v dd =v out +2.0v, c w =0.01f 50 120 250 ms t wr reset hold time of wdt v dd =v out +2.0v, c w =0.01f 5 12 25 ms v ihsck sck input voltage "h" v dd =v out +2.0v 0.8 v out v dd v 1.8v v out 2.9v 0 0.1 v out v ilsck sck input voltage "l" v dd =v out +2.0v 3.0v v out 5.0v 0 0.2 v out v v ihce ce input voltage "h" 1.2 v dd v v ilce ce input voltage "l" 0.0 0.2 v i ihsck sck input current "h" v dd =sck=v out +2.0v -1 1 a i ilsck sck input current "l" v dd =v out +2.0v, sck=gnd -1 1 a r pu ce pull-up resistance 2 4 10 m i cd c d pin output current v dd =1.5v, v ds =0.5v 1 2 ma i ctw c tw pin output current v dd =1.5v, v ds =0.5v 1 2 ma i reset reset pin output current v dd =1.5v, v ds =0.5v 1 2 ma i leak reset pin leakage current v dd =10.0v, ce=gnd, v ds =10.0v -1 1 a
r5101g 6 symbol item conditions min. typ. max. unit t sckw sck input pulse width v dd =v out +2.0v 500 ns v start minimum operating voltage of voltage detector 0.9 1.5 v ? 1) in case that v out <2v, please use i out with 0.1ma or more. ? dropout voltage by output voltage topt = 25c recommended operating conditions (electrical characteristics) all of electronic equipment should be designed that the mounted semiconductor devices operate within the recommended operating conditions. the semiconductor devices cannot operate normally over the recommended operating conditions, even if when they are used over such conditions by momentary electronic noise or surge. and the semiconductor de vices may receive serious damage when they continue to operate over the recommended operating conditions. dropout voltage v dif (v) output voltage v out (v) condition min. typ. max. 1.8 v out 2.9 i out = 10ma 0.100 0.350 0.650 3.0 v out 3.9 0.100 0.500 0.850 4.0 v out 5.0 i out = 30ma 0.100 0.350 0.650
r5101g 7 typical applications r5101gxxxseries con. sck c d c tw v dd reset ce gnd v out reset d out 510k 1 f 1 f c w (0.01 f) c d (0.001 f) v dd technical notes the minimum value of the operation margin for rele asing the voltage detector is specified as 0.02v. this ic is sensing the output voltage of the regulator of this ic itself, and depending on the input voltage transient or load transient, the operation margin may be disappeared. the power line noise may cause a mis-operat ion of the watchdog timer, therefore v dd and gnd lines must be sufficient enough for avoiding the mis-operation. if the power line has some noise, the output of the regulato r of this ic may generate the noise, in such a case, the built-in detector may detect the output noise of the voltage regulator and reset signal may output. to prevent the ic from this kind of mis-operation, we recommend using a capacitor in the capacitance range from 1 f to 2.2 f between v out pin and gnd pin. to avoid the mis-operation, during watchdog timer monitori ng time, there is some ignoring time against clock pulse. therefore, during the ignoring time, input clock pulse (rising edge trigger) is ignored. the ignoring time is approximately as follows: 1) the time interval for v ctw pin voltage from vref2h to (vref2h-vref2h/20) 2) the time interval for v ctw pin voltage from vref2l+vref2l/20 to vref2l
r5101g 8 timing chart 1 2 3 4 5 5 6 7 6 7 5 8 2 3 5 9 9 8 v dd vstart v out +v det -v det t pr t sckw t wr detector threshold hysteresis t wd v cd vref2h v ctw vref2l vref2h v sck v ce v reset
r5101g 9 operation 1 when v dd is turned on and input voltage reaches vs tart (nearly equal 0.8v), the output of reset pin becomes "l" level. 2 an external capacitor starts to be charged through the c d pin when an output voltage of the voltage regulator, v out , crosses the released voltage, +v det , from lower to higher. the v reset is kept "l" level until voltage of the c d pin, v cd , reaches to the vref2h, and after that the v reset becomes to "h" level. ? t pr : time interval between the timing of starting edge of forcing voltage to v dd pin and the timing of reverse the voltage level of v reset . t pr can be set by connecting an external capacitor to c d pin, t pr can be calculated as shown below; t pr (ms) 14000 c d (f); c d means a value of an external capacitor connected to c d pin. 3 when the voltage level of v cd reaches to the vref2h, the external ca pacitor starts to be charged through the c tw pin and the watchdog timer begins to operate. 4 the operation mode for the external capacitor changes from charging mode to discharging mode through c tw pin when the voltage level of c tw pin, v ctw , reaches to the vref2h. 5 while the c tw pin is on the discharging mode, if a clock pulse is entered (synchronous with a rising edge of the pulse), the operation mode of c tw pin changes from discharging mode to charging mode. and the external capacitor connected to c tw pin is charged until its voltage level reaches to vref2h. 6 while the c tw pin is on the discharging mode, if v ctw level drops to vref2l without clock pulse to clk pin, the voltage level of reset pin becomes from "h" to "l". ? watchdog timeout period, t wd ,: discharging time of c tw pin level from vref2h to vref2l t wd can be set by connecting an external capacitor to c w pin, t wd can be calculated as shown below; t wd (ms) 12000 c w (f); c w means a value of an external capacitor connected to c w pin. 7 c tw pin is changed to charging mode from discharg ing mode when the reset signal is generated. ? reset timeout period of the watchdog timer, t wr ,: time interval between charging time of the c tw pin from vref2l to vref2h. t wr can be calculated by the next equation as shown below; t wr (ms) t wd /10 8 the output voltage level of reset pin becomes from "h" to "l", or a reset signal is generated when an output voltage of the voltage regulator drops to a level at equal or less than -v det . 9 the watchdog timer will be halted when a voltage level of ce pin becomes to "l". in this case, only the watchdog timer is stopped and monitoring the output volt age is continued. after that, if the voltage level of ce pin becomes to "h", c tw pin starts to be on charging mode.
r5101g 10 test circuit supply current test circuit output voltage test circuit reset gnd ce a v out sck c d c tw v dd reset gnd ce v v out i out sck c d c tw v dd detector threshold(v det ) test circuit reset and watchdog timeout periods test circuit 470k reset gnd ce v out sck c d c tw v dd v oscilloscope 470k reset gnd ce v out sck c d c tw v dd sck input current test circuit output current test circuit reset gnd ce v out sck c d c tw v dd a reset gnd ce v out sck c d c tw v dd a reset output leakage current test ci rcuit minimum input voltage for reset output test circuit reset gnd ce v out sck c d c tw v dd a reset gnd ce v out sck c d c tw v dd 470k v
r5101g 11 typical characteristics 1) output voltage vs. output current r5101g (vr=3v) r5101g (vr=5v) 2.0 3.5 3.0 2.5 1.5 0.5 1.0 0.0 output current i out (ma) 0 85c 25c -40c 100 150 200 50 output voltage v out (v) v dd =5v 4.0 6.0 5.0 3.0 1.0 2.0 0.0 output current i out (ma) 0 100 85c 0c -40c 300 400 200 output voltage v out (v) v dd =7v 2) output voltage vs. input voltage r5101g (vr=3v) r5101g (vr=5v) 3.2 3.1 3.0 2.9 2.8 input voltage v dd (v) 23 5 7 68910 4 output voltage v out (v) topt =25c 30ma 0ma 10ma 5.2 5.1 5.0 4.9 4.8 45 79 810 6 input voltage v dd (v) output voltage v out (v) topt =25c 0ma 10ma 30ma 3) dropout voltage vs. output current r5101g (vr=3v) r5101g (vr=5v) 0.6 1.0 0.8 0.2 0.4 0.0 output current i out (ma) 0 30 20 40 10 dropout voltage v dif (v) 85c 25c -40c 0.4 0.6 0.8 1.0 0.2 0.0 output current i out (ma) 10 20 40 50 30 dropout voltage v dif (v) v dd =7.0v 85c 25c -40c
r5101g 12 4) output voltage vs. temperature r5101g (vr=3v) r5101g (vr=5v) 3.10 3.00 2.90 3.05 2.95 temperature topt (c) -50 50 100 0 -25 75 25 output voltage v out (v) v dd =5v 5.10 5.00 4.90 5.05 4.95 temperature topt (c) -50 50 100 0 -25 75 25 output voltage v out (v) v dd =7.0v, i out =10ma 5) reset pin voltage vs. input voltage 6) detector threshold vs. temperature r5101g (vd=2.7v) r5101g (vd=2.7v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 input voltage v dd (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 reset pin voltage v reset (v) pull-up 510k 85c -40c 25c 2.90 2.80 2.75 2.60 2.85 +vdet -vdet 2.70 2.65 temperature topt (c) -50 50 100 0 -25 75 25 detector threshold v det (v) 7) c d pin output current vs. input voltage 8) c tw pin output current vs. input voltage r5101g (vd=2.7v) r5101g (vd=2.7v) 0 2 4 6 8 10 12 input voltage v dd (v) 0123 c d output current i out (ma) v ds =0.5v 85c 25c -40c 8 12 10 6 2 4 0 input voltage v dd (v) 01 0.5 2.5 1.5 2 3.0 c tw output current i out (ma) v ds =0.5v 85c 25c -40c
r5101g 13 9) reset pin output current vs. input voltage 10) delay time of released voltage vs. temperature r5101g (vd=2.7v) r5101g 85 c 25 c -40 c 0 2 4 6 8 10 12 input voltage v dd (v) 0123 reset output current i out (ma) v ds =0.5v 0 2 4 8 12 18 6 10 14 16 20 22 input voltage v dd (v) -50 0 -25 50 25 100 75 delay time of release voltage t pr (ms) 11) watchdog timeout period vs. temperature 12) reset timeout period vs. temperature r5101g r5101g 0 20 40 60 80 100 120 140 160 temperature topt ( c ) -50 0 -25 50 75 25 100 watchdog timeout period t wd (ms) 10 16 12 14 8 2 4 6 0 -50 -25 25 75 50 100 0 temperature topt (c) reset timeout period t wr (ms) 13) t pr vs. external capacitance of c d pin 14) t wd , t wr vs. external capacitance of c tw pin 1 10 100 1000 10000 100000 c d external capacitance pin (f) 1.e-09 1.e-08 1.e-07 1.e-06 t pr (ms) 0.1 10 1 100 1000 10000 100000 c tw external capacitance pin (f) 1.e-08 1.e-07 t wd t wr 1.e-06 t wd ,t wr (ms)
r5101g 14 15) ce pull-up resistance vs. temperature r5101g 10 9 8 7 6 5 4 3 2 1 0 temperature topt (c) -50 50 100 0 -25 75 25 ce pull-up resistance r pu (m ) 16) supply current vs. input voltage (wdt on) 17) supply current vs. temperature (wdt on) r5101g r5101g 0 3 6 9 12 15 input voltage v dd (v) 36 5 489 710 supply current lss-on ( a) topt=25 c 12 15 6 9 3 0 temperature topt (c) -50 50 100 0 -25 75 25 supply current iss-off ( a) v dd =5v 18) supply current vs. input voltage (wdt off) 19) supply current vs. temperature (wdt off) r5101g r5101g 0 3 6 9 12 15 18 input voltage v dd (v) 36 5 489 710 supply current lss-off ( a) topt=25 c 12 18 15 6 9 3 0 temperature topt (c) -50 50 100 0 -25 75 25 supply current iss-off ( a) v dd =5v
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